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383d11c2ac9254836f8107e4a2fa6901b7bccd09
YosysHQ.yosys
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techlibs
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intel
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Richard Herveille
2893938355
Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
..
common
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cyclone10lp
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cycloneiv
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cycloneive
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max10
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Makefile.inc
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synth_intel.cc
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