github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-20 20:52:52 +00:00
Code Issues Releases Wiki Activity
Files
3870976bccd561fa33100cca57eaff4e16bc58d3
YosysHQ.yosys/techlibs/analogdevices
History
Lofty 3870976bcc analogdevices: update timing model
2025-11-12 22:44:12 +00:00
..
abc9_model.v
Create synth_analogdevices
2025-11-12 22:44:11 +00:00
arith_map.v
analogdevices: update timing model
2025-11-12 22:44:12 +00:00
brams_defs.vh
Create synth_analogdevices
2025-11-12 22:44:11 +00:00
brams_map.v
Create synth_analogdevices
2025-11-12 22:44:11 +00:00
brams.txt
Create synth_analogdevices
2025-11-12 22:44:11 +00:00
cells_map.v
Create synth_analogdevices
2025-11-12 22:44:11 +00:00
cells_sim.v
analogdevices: update timing model
2025-11-12 22:44:12 +00:00
cells_xtra.py
Create synth_analogdevices
2025-11-12 22:44:11 +00:00
cells_xtra.v
analogdevices: remove some extra cells!
2025-11-12 22:44:12 +00:00
dsp_map.v
Create synth_analogdevices
2025-11-12 22:44:11 +00:00
ff_map.v
test suite
2025-11-12 22:44:11 +00:00
lut_map.v
analogdevices: update timing model
2025-11-12 22:44:12 +00:00
lutrams_map.v
Create synth_analogdevices
2025-11-12 22:44:11 +00:00
lutrams.txt
test suite
2025-11-12 22:44:11 +00:00
Makefile.inc
Create synth_analogdevices
2025-11-12 22:44:11 +00:00
mux_map.v
Create synth_analogdevices
2025-11-12 22:44:11 +00:00
retarget_map.v
analogdevices: user retargeting
2025-11-12 22:44:12 +00:00
synth_analogdevices.cc
analogdevices: update timing model
2025-11-12 22:44:12 +00:00