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3a51714451dbd5a0aec5d5167429f899950f2c4e
YosysHQ.yosys
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frontends
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ast
History
Clifford Wolf
3a51714451
Fix error for wire decl in always block,
fixes
#763
...
Signed-off-by: Clifford Wolf <
clifford@clifford.at
>
2019-03-02 11:56:44 -08:00
..
ast.cc
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
ast.h
Use mem2reg on memories that only have constant-index write ports
2019-03-01 13:35:09 -08:00
dpicall.cc
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
genrtlil.cc
Fix error for wire decl in always block,
fixes
#763
2019-03-02 11:56:44 -08:00
Makefile.inc
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
simplify.cc
Fix $global_clock handling vs autowire
2019-03-02 10:38:13 -08:00
