Krystine Sherwin 3d08ed216d QLF_TDP36K: parameterised sim test gen ...

Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.

2023-12-04 15:52:03 +01:00

..

aiger

…

arch

QLF_TDP36K: parameterised sim test gen

2023-12-04 15:52:03 +01:00

asicworld

…

bind

Add support for parsing the SystemVerilog 'bind' construct

2021-07-16 09:31:39 -04:00

blif

Adding check for BLIF names command input plane size.

2022-08-21 23:18:20 -05:00

bram

Fix the tests we just broke

2021-12-10 00:22:37 +01:00

errors

…

fmt

cxxrtl: reorganize runtime component files.

2023-11-28 15:32:36 +00:00

fsm

…

hana

…

liberty

fix file rights

2023-05-17 13:39:57 +02:00

lut

…

memfile

…

memlib

memory_libmap: look for ram_style attributes on surrounding signals

2023-10-19 19:23:35 +02:00

memories

Fix the tests we just broke

2021-12-10 00:22:37 +01:00

opt

opt_expr: Fix 'signed X>=0' replacement for wide output ports

2023-08-01 13:50:12 +01:00

opt_share

…

proc

proc_clean: only consider fully-defined switch operands too.

2023-08-12 02:46:31 +02:00

realmath

…

rpc

…

sat

Proper example code

2022-03-14 15:39:11 +01:00

select

…

share

…

sim

Replace GNU specific invocation of basename(1) with the equivalent

2022-10-23 11:02:18 +13:00

simple

test: add tests for shiftadd and shiftmul

2023-11-06 14:01:37 +01:00

simple_abc9

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

smv

…

sva

Fix sva_value_change_changed test for updated verific

2023-10-03 11:46:43 +02:00

svinterfaces

Resolve package types in interfaces (#3658)

2023-02-12 18:25:39 -05:00

svtypes

Corrected handling of nested typedefs of struct/union

2023-07-20 23:39:44 -04:00

techmap

booth: Extend test to catch bug from previous commit

2023-10-04 23:30:29 +02:00

tools

support file locations containing spaces

2022-08-08 20:30:50 +02:00

unit

…

various

ast: use new format string helpers.

2023-08-11 04:46:52 +02:00

verific

verific: import attributes on ports

2023-10-20 18:31:41 +02:00

verilog

fix width of post-increment/decrement expressions

2023-09-18 23:46:06 -04:00

vloghtb

Use HTTPS for website links, gatecat email

2021-06-09 12:16:56 +02:00

xprop

xprop tests: Make iverilog invocation more portable

2023-02-13 16:54:11 +01:00

gen-tests-makefile.sh

Out of bounds checking for struct/union members

2023-02-19 23:25:08 +01:00