YosysHQ.yosys

mirror of synced 2026-01-21 10:23:03 +00:00

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whitequark ca866d384e write_verilog: handle the $shift cell.

The implementation corresponds to the following Verilog, which is
lifted straight from simlib.v:

    module \\$shift (A, B, Y);

    parameter A_SIGNED = 0;
    parameter B_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter B_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [Y_WIDTH-1:0] Y;

    generate
        if (B_SIGNED) begin:BLOCK1
            assign Y = $signed(B) < 0 ? A << -B : A >> B;
        end else begin:BLOCK2
            assign Y = A >> B;
        end
    endgenerate

    endmodule

2018-12-16 18:46:32 +00:00

aiger

Add "write_aiger -I -O -B"

2018-11-12 09:27:33 +01:00

blif

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

btor

Fix btor init value handling

2018-12-08 06:21:31 +01:00

edif

Add "write_edif -attrprop"