12 lines
352 B
Verilog
12 lines
352 B
Verilog
// After performing sequential synthesis, map the synchronous flops back to
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// standard MISTRAL_FF flops.
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module $__MISTRAL_FF_SYNCONLY (
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input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA,
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output reg Q
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);
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MISTRAL_FF _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ACLR(1'b1), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q));
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endmodule
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