github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-15 08:22:36 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/techlibs/nexus
History
gatecat 7bac1920b2 nexus: Fix BRAM write enable in PDP mode 
Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-04 17:59:36 +01:00
..
arith_map.v
nexus: Fix arith_map CO signal.
2022-02-06 13:05:30 +01:00
brams_map.v
nexus: Fix BRAM write enable in PDP mode
2023-01-04 17:59:36 +01:00
brams.txt
nexus: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
cells_map.v
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
cells_sim.v
nexus: Fix BB sim model
2022-01-19 18:14:24 +00:00
cells_xtra.py
nexus: Add DSP simulation model
2020-11-18 10:21:17 +00:00
cells_xtra.v
nexus: Add DSP simulation model
2020-11-18 10:21:17 +00:00
dsp_map.v
nexus: DSP inference support
2020-11-20 08:45:55 +00:00
latches_map.v
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
lrams_map.v
nexus: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lrams.txt
nexus: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams_map.v
nexus: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams.txt
nexus: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Makefile.inc
nexus: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
parse_init.vh
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
synth_nexus.cc
nexus: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00