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YosysHQ.yosys/tests/various/constmsk_test.v
2014-09-04 15:07:30 +02:00

5 lines
133 B
Verilog

module test(input [3:0] A, output [3:0] Y1, Y2);
assign Y1 = |{A[3], 1'b0, A[1]};
assign Y2 = |{A[2], 1'b1, A[0]};
endmodule