18 lines
255 B
Plaintext
18 lines
255 B
Plaintext
read_verilog <<EOT
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(* blackbox *)
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module bb(input i, output o);
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endmodule
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(* whitebox *)
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module wb(input i, output o);
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assign o = ~i;
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endmodule
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module top(input i, output o);
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assign o = ~i;
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endmodule
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EOT
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design -stash gate
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design -import gate -as gate
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