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mirror of synced 2026-01-17 09:02:38 +00:00
YosysHQ.yosys/tests/verilog/include_self.ys
Zachary Snow 1ec5994100 verilog: fix handling of nested ifdef directives
- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
2021-03-01 12:28:33 -05:00

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read_verilog include_self.v
select -assert-count 1 top/x