1
0
mirror of synced 2026-01-17 09:02:38 +00:00
YosysHQ.yosys/tests/verilog/struct_access.ys
Zachary Snow a9c8ca21d5 sv: fix two struct access bugs
- preserve signedness of struct members
- fix initial width detection of struct members (e.g., in case expressions)
2021-07-15 11:57:20 -04:00

5 lines
101 B
Plaintext

read_verilog -formal -sv struct_access.sv
proc
opt -full
sat -verify -seq 1 -prove-asserts -show-all