Udi Finkelstein 73d426bc87 Modified errors into warnings ...

No longer false warnings for memories and assertions

2018-06-05 18:03:22 +03:00

..

.gitignore

Added tests/various/.gitignore

2014-07-26 17:43:41 +02:00

constmsk_test.v

Added tests/various/constmsk_test.ys

2014-09-04 15:07:30 +02:00

constmsk_test.ys

Added tests/various/constmsk_test.ys

2014-09-04 15:07:30 +02:00

constmsk_testmap.v

Added tests/various/constmsk_test.ys

2014-09-04 15:07:30 +02:00

muxcover.ys

Added "pmuxtree" command

2015-04-07 20:27:10 +02:00

reg_wire_error.sv

Modified errors into warnings

2018-06-05 18:03:22 +03:00

reg_wire_error.ys

reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files

2018-06-05 18:00:06 +03:00

run-test.sh

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submod_extract.ys

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