This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-04-19 18:53:16 +00:00
Code
Issues
Releases
Wiki
Activity
Files
40af327cb6944f89af80a4b2ac4fc5ba4674d5d7
YosysHQ.yosys
/
backends
/
verilog
History
Akash Levy
ace558e90c
Simplify using module->ports, which is apparently sorted
2024-11-17 11:36:30 -08:00
..
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
verilog_backend.cc
Simplify using module->ports, which is apparently sorted
2024-11-17 11:36:30 -08:00