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41107e5473f117d9314dca6b0bfb140612c130fb
YosysHQ.yosys
/
techlibs
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intel
History
Richard Herveille
2893938355
Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
..
common
Fixed data/address width parameters
2024-03-06 02:45:07 +01:00
cyclone10lp
…
cycloneiv
…
cycloneive
…
max10
Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
Makefile.inc
…
synth_intel.cc
removed commented out code
2024-03-15 01:48:22 +01:00