github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-08 16:57:58 +00:00
Code Issues Releases Wiki Activity
Files
41b41fefb38900e12e709137a35565cceb0bf02b
YosysHQ.yosys/tests/sim
History
Jannis Harder 6a0ee6e4fb Revert sim's cycle_width default back to 10, but keep -width option
2025-10-20 14:40:05 +02:00
..
tb
test dlatchsr and adlatch
2022-02-16 13:58:51 +01:00
.gitignore
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
adff.v
Added test cases
2022-02-16 13:27:59 +01:00
adffe.v
Added test cases
2022-02-16 13:27:59 +01:00
adlatch.v
Added test cases
2022-02-16 13:27:59 +01:00
aldff.v
Added test cases
2022-02-16 13:27:59 +01:00
aldffe.v
Added test cases
2022-02-16 13:27:59 +01:00
assume_x_first_step.ys
Assume x values for missing signal data in FST
2024-10-02 12:08:48 +02:00
dff.v
Added test cases
2022-02-16 13:27:59 +01:00
dffe.v
Added test cases
2022-02-16 13:27:59 +01:00
dffsr.v
Added test cases
2022-02-16 13:27:59 +01:00
dlatch.v
Added test cases
2022-02-16 13:27:59 +01:00
dlatchsr.v
test dlatchsr and adlatch
2022-02-16 13:58:51 +01:00
run-test.sh
test: restore verific handling, nicer naming
2024-12-13 10:24:47 +01:00
sdff.v
Added test cases
2022-02-16 13:27:59 +01:00
sdffce.v
Added test cases
2022-02-16 13:27:59 +01:00
sdffe.v
Added test cases
2022-02-16 13:27:59 +01:00
sim_adff.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_adffe.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_adlatch.ys
test dlatchsr and adlatch
2022-02-16 13:58:51 +01:00
sim_aldff.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_aldffe.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_cycles.ys
Revert sim's cycle_width default back to 10, but keep -width option
2025-10-20 14:40:05 +02:00
sim_dff.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_dffe.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_dffsr.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_dlatch.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_dlatchsr.ys
test dlatchsr and adlatch
2022-02-16 13:58:51 +01:00
sim_sdff.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_sdffce.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_sdffe.ys
Added test cases
2022-02-16 13:27:59 +01:00
simple_assign.v
Assume x values for missing signal data in FST
2024-10-02 12:08:48 +02:00
simple_assign.vcd
Assume x values for missing signal data in FST
2024-10-02 12:08:48 +02:00
var_reference_with_whitespace.vcd
Fix: handle VCD variable references with and without whitespace
2024-10-01 11:51:20 +02:00
var_reference_without_whitespace.vcd
Fix: handle VCD variable references with and without whitespace
2024-10-01 11:51:20 +02:00
vcd_var_reference_whitespace.ys
Fix: handle VCD variable references with and without whitespace
2024-10-01 11:51:20 +02:00
vector_assign.il
Fix: handle VCD variable references with and without whitespace
2024-10-01 11:51:20 +02:00