Clifford Wolf 088f9c9cab Fix verilog pre-processor for multi-level relative includes

2017-03-14 17:30:20 +01:00

..

.gitignore

Updated .gitignore file for ilang and verilog frontends

2014-10-15 01:14:38 +02:00

const2ast.cc

Fixed segfault on invalid verilog constant 1'b_

2015-09-22 08:13:09 +02:00

Makefile.inc

Adjust makefiles to work with out-of-tree builds

2015-08-12 15:04:44 +02:00

preproc.cc

Fix verilog pre-processor for multi-level relative includes

2017-03-14 17:30:20 +01:00

verilog_frontend.cc

Added "verilog_defines" command

2016-12-15 17:49:28 +01:00

verilog_frontend.h

Remember global declarations and defines accross read_verilog calls

2016-11-15 12:42:43 +01:00

verilog_lexer.l

Add $live and $fair cell types, add support for s_eventually keyword

2017-02-25 10:36:39 +01:00

verilog_parser.y

Allow $anyconst, etc. in non-formal SV mode

2017-03-01 10:47:05 +01:00