Eddie Hung 4290548de3 Make abc9 test a bit more interesting

2019-08-30 20:31:53 -07:00

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aiger

tests: use optional ABCEXTERNAL when specified

2019-06-27 23:00:13 -04:00

arch

Add simcells.v, simlib.v, and some output

2019-06-27 11:13:49 -07:00

asicworld

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00

bram

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errors

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

fsm

Speed up "make test" and related cleanups

2019-08-17 14:37:07 +02:00

hana

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ice40

macc test fix

2019-08-30 16:01:36 +03:00

liberty

Liberty file parser now accepts superfluous ;

2019-03-27 15:16:19 +01:00

lut

Forgot to commit

2019-07-16 12:44:26 -07:00

memories

memory_dff: Fix checking of feedback mux input when more than one mux

2019-07-02 13:35:50 +01:00

opt

Respect opt_expr -keepdc as per @cliffordwolf

2019-08-22 08:37:27 -07:00

opt_share

Support various binary operators in opt_share

2019-08-04 19:06:38 +02:00

proc

proc_clean: fix order of switch insertion.

2019-08-19 16:44:23 +00:00

realmath

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sat

Revert to using clean

2019-08-27 09:24:32 -07:00

share

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simple

Add test case for real parameters

2019-08-20 11:38:21 +02:00

simple_abc9

Nicer formatting

2019-08-29 17:24:48 -07:00

smv

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sva

Fix "verific -extnets" for more complex situations

2019-03-26 14:17:46 +01:00

svinterfaces

Fix typo in tests/svinterfaces/runone.sh

2019-05-03 14:40:51 +02:00

techmap

improve clkbuf_inhibit propagation upwards through hierarchy

2019-08-27 17:26:47 +02:00

tools

autotest.sh to define _AUTOTB when test_autotb

2019-06-28 14:56:22 -07:00

unit

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various

Make abc9 test a bit more interesting

2019-08-30 20:31:53 -07:00

vloghtb

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xilinx

Add .gitignore

2019-08-28 09:55:34 -07:00