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43396fae2c03b876557a73d3f3c19f4cd5161251
YosysHQ.yosys
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backends
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Claire Wolf
50d70288d0
Preserve wires with keep attribute in EDIF back-end
...
Signed-off-by: Claire Wolf <
clifford@clifford.at
>
2020-01-29 14:07:11 +01:00
..
aiger
write_xaiger: fix for (* keep *) on flop output
2020-01-21 09:43:04 -08:00
blif
…
btor
Use cell name for btor bad state props when it is a public name
2019-11-14 11:57:38 +01:00
edif
Preserve wires with keep attribute in EDIF back-end
2020-01-29 14:07:11 +01:00
firrtl
Merge pull request
#1258
from YosysHQ/eddie/cleanup
2019-08-10 09:52:14 +02:00
ilang
…
intersynth
…
json
…
protobuf
Add aiger and protobuf backends binary support
2019-09-28 09:51:48 +02:00
simplec
…
smt2
Improve yosys-smtbmc "solver not found" handling
2020-01-27 17:48:56 +01:00
smv
…
spice
…
table
…
verilog
write_verilog: add -extmem option, to write split memory init files.
2019-11-18 01:27:21 +00:00
