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446ccf1f05b2b36db9161bf4ab050778a1cbaee6
YosysHQ.yosys
/
frontends
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verilog
History
Clifford Wolf
34005348b6
Bugfix in verilog_defaults argument parser
2017-12-24 17:21:37 +01:00
..
.gitignore
Updated .gitignore file for ilang and verilog frontends
2014-10-15 01:14:38 +02:00
const2ast.cc
Fixed segfault on invalid verilog constant 1'b_
2015-09-22 08:13:09 +02:00
Makefile.inc
Adjust makefiles to work with out-of-tree builds
2015-08-12 15:04:44 +02:00
preproc.cc
Accommodate Windows-style paths during include-file processing.
2017-11-14 16:16:24 -05:00
verilog_frontend.cc
Bugfix in verilog_defaults argument parser
2017-12-24 17:21:37 +01:00
verilog_frontend.h
Remember global declarations and defines accross read_verilog calls
2016-11-15 12:42:43 +01:00
verilog_lexer.l
Add Verilog "automatic" keyword (ignored in synthesis)
2017-11-23 08:51:38 +01:00
verilog_parser.y
Add Verilog "automatic" keyword (ignored in synthesis)
2017-11-23 08:51:38 +01:00