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YosysHQ.yosys/tests/asicworld
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Clifford Wolf 964a67ac41 Added note to "make test": use git checkout of iverilog
2014-07-16 10:03:07 +02:00
..
.gitignore
added more .gitignore files (make test)
2013-01-05 11:35:52 +01:00
code_hdl_models_arbiter_tb.v
initial import
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code_hdl_models_arbiter.v
initial import
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code_hdl_models_cam.v
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code_hdl_models_clk_div_45.v
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code_hdl_models_clk_div.v
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code_hdl_models_d_ff_gates.v
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code_hdl_models_d_latch_gates.v
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code_hdl_models_decoder_2to4_gates.v
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code_hdl_models_decoder_using_assign.v
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code_hdl_models_decoder_using_case.v
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code_hdl_models_dff_async_reset.v
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code_hdl_models_dff_sync_reset.v
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code_hdl_models_dlatch_reset.v
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code_hdl_models_encoder_4to2_gates.v
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code_hdl_models_encoder_using_case.v
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code_hdl_models_encoder_using_if.v
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code_hdl_models_full_adder_gates.v
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code_hdl_models_full_subtracter_gates.v
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code_hdl_models_gray_counter.v
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code_hdl_models_GrayCounter.v
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code_hdl_models_half_adder_gates.v
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code_hdl_models_lfsr_updown.v
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code_hdl_models_lfsr.v
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code_hdl_models_misc1.v
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code_hdl_models_mux21_switch.v
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code_hdl_models_mux_2to1_gates.v
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code_hdl_models_mux_using_assign.v
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code_hdl_models_mux_using_case.v
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code_hdl_models_mux_using_if.v
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code_hdl_models_nand_switch.v
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code_hdl_models_one_hot_cnt.v
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code_hdl_models_parallel_crc.v
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code_hdl_models_parity_using_assign.v
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code_hdl_models_parity_using_bitwise.v
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code_hdl_models_parity_using_function.v
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code_hdl_models_pri_encoder_using_assign.v
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code_hdl_models_ram_sp_ar_sw.v
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code_hdl_models_ram_sp_sr_sw.v
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code_hdl_models_rom_using_case.v
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code_hdl_models_serial_crc.v
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code_hdl_models_t_gate_switch.v
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code_hdl_models_tff_async_reset.v
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code_hdl_models_tff_sync_reset.v
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code_hdl_models_uart.v
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code_hdl_models_up_counter_load.v
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code_hdl_models_up_counter.v
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code_hdl_models_up_down_counter.v
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code_specman_switch_fabric.v
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code_tidbits_asyn_reset.v
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code_tidbits_blocking.v
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code_tidbits_fsm_using_always.v
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code_tidbits_fsm_using_function.v
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code_tidbits_fsm_using_single_always.v
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code_tidbits_nonblocking.v
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code_tidbits_reg_combo_example.v
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code_tidbits_reg_seq_example.v
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code_tidbits_syn_reset.v
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code_tidbits_wire_example.v
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code_verilog_tutorial_addbit.v
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code_verilog_tutorial_always_example.v
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code_verilog_tutorial_bus_con.v
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code_verilog_tutorial_comment.v
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code_verilog_tutorial_counter_tb.v
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code_verilog_tutorial_counter.v
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code_verilog_tutorial_d_ff.v
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code_verilog_tutorial_decoder_always.v
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code_verilog_tutorial_decoder.v
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code_verilog_tutorial_escape_id.v
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code_verilog_tutorial_explicit.v
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code_verilog_tutorial_first_counter_tb.v
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code_verilog_tutorial_first_counter.v
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code_verilog_tutorial_flip_flop.v
initial import
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code_verilog_tutorial_fsm_full_tb.v
Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
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code_verilog_tutorial_fsm_full.v
initial import
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code_verilog_tutorial_good_code.v
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code_verilog_tutorial_if_else.v
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code_verilog_tutorial_multiply.v
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code_verilog_tutorial_mux_21.v
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code_verilog_tutorial_n_out_primitive.v
initial import
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code_verilog_tutorial_parallel_if.v
initial import
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code_verilog_tutorial_parity.v
initial import
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code_verilog_tutorial_simple_function.v
initial import
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code_verilog_tutorial_simple_if.v
initial import
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code_verilog_tutorial_task_global.v
initial import
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code_verilog_tutorial_tri_buf.v
initial import
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code_verilog_tutorial_v2k_reg.v
initial import
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code_verilog_tutorial_which_clock.v
initial import
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README
initial import
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run-test.sh
Added note to "make test": use git checkout of iverilog
2014-07-16 10:03:07 +02:00

README 

Borrowed verilog examples from http://www.asic-world.com/.
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