Emil J 4b8d42d22c Merge pull request #5095 from YosysHQ/emil/one-bit-width ...

rtlil: enable single-bit vector wires

2025-05-23 15:55:45 +02:00

..

aiger

driver: allow --no-version still write things like Generated by Yosys

2025-05-07 11:34:23 +02:00

aiger2

abc_new: Fix PI confusion in whitebox model export

2024-12-10 14:27:29 +01:00

blif

driver: allow --no-version still write things like Generated by Yosys

2025-05-07 11:34:23 +02:00

btor

driver: allow --no-version still write things like Generated by Yosys

2025-05-07 11:34:23 +02:00

cxxrtl

cxxrtl: fix missing sign extension before shift operation for signed values

2025-05-03 09:38:16 +00:00

edif

driver: allow --no-version still write things like Generated by Yosys

2025-05-07 11:34:23 +02:00

firrtl

Reinstate #4768

2025-04-08 11:58:05 +12:00

functional

smtr: Refactor write back into _eval and _initial

2025-02-07 13:58:09 +13:00

intersynth

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

jny

driver: allow --no-version still write things like Generated by Yosys

2025-05-07 11:34:23 +02:00

json

driver: allow --no-version still write things like Generated by Yosys

2025-05-07 11:34:23 +02:00

rtlil

driver: allow --no-version still write things like Generated by Yosys

2025-05-07 11:34:23 +02:00

simplec

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

smt2

driver: allow --no-version still write things like Generated by Yosys

2025-05-07 11:34:23 +02:00

smv

driver: allow --no-version still write things like Generated by Yosys

2025-05-07 11:34:23 +02:00

spice

driver: allow --no-version still write things like Generated by Yosys

2025-05-07 11:34:23 +02:00

table

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

verilog

Merge pull request #5095 from YosysHQ/emil/one-bit-width

2025-05-23 15:55:45 +02:00