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YosysHQ.yosys/tests
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clairexen 66afed6f55
Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef 
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
2020-07-28 12:56:22 +02:00
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aiger
tests: aiger test for wire->start_offset != 0
2020-05-02 10:00:32 -07:00
arch
intel_alm: direct M10K instantiation
2020-07-27 15:39:06 +02:00
asicworld
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bram
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errors
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fsm
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
hana
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liberty
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
lut
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memfile
Added 'set -e' into tests/memfile/run-test.sh
2020-02-06 10:45:40 -03:00
memories
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opt
clk2fflogic: Support all FF types.
2020-07-24 03:19:48 +02:00
opt_share
Support various binary operators in opt_share
2019-08-04 19:06:38 +02:00
proc
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
realmath
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rpc
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
sat
satgen: Add support for dffe, sdff, sdffe, sdffce cells.
2020-07-24 03:19:21 +02:00
select
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 15:35:05 -07:00
share
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simple
Expand tests/simple/constmuldivmod.v
2020-05-28 22:59:04 +02:00
simple_abc9
abc9: test to use box file instead of auto
2020-05-14 10:33:56 -07:00
smv
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sva
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svinterfaces
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svtypes
static cast: add tests
2020-06-19 17:40:38 -07:00
techmap
zinit: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
tools
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unit
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various
Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef
2020-07-28 12:56:22 +02:00
verilog
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings
2020-06-03 08:37:07 -07:00
vloghtb
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