github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-24 03:27:10 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/tests
History
Marcelina Kościelnicka 835688bf80 opt_mem_feedback: Rewrite feedback path finding logic. 
Fixes #2766.
2021-05-24 23:20:30 +02:00
..
aiger
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
arch
intel_alm: Fix illegal carry chains
2021-05-15 22:37:06 +01:00
asicworld
…
blif
tests/blif: Add missing gitignore
2021-05-20 12:49:51 +02:00
bram
tests/bram: Do not generate write address collisions.
2021-03-08 16:53:03 +01:00
errors
…
fsm
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
hana
…
liberty
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
lut
…
memfile
…
memories
tests: Parallelize
2020-09-21 15:07:02 +02:00
opt
opt_mem_feedback: Rewrite feedback path finding logic.
2021-05-24 23:20:30 +02:00
opt_share
tests: Parallelize
2020-09-21 15:07:02 +02:00
proc
proc_arst: Add special-casing of clock signal in conditionals.
2021-03-15 17:17:29 +01:00
realmath
…
rpc
…
sat
assertpmux: Fix crash on unused $pmux output.
2021-02-22 23:30:28 +01:00
select
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 15:35:05 -07:00
share
…
simple
verilog: fix buf/not primitives with multiple outputs
2021-03-17 11:44:03 -04:00
simple_abc9
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
smv
…
sva
…
svinterfaces
…
svtypes
verilog: check entire user type stack for type definition
2021-03-21 19:35:13 -04:00
techmap
Add tests for some common techmap files.
2021-02-24 01:07:34 +01:00
tools
memory_dff: Remove now-useless write port handling.
2021-03-08 20:16:29 +01:00
unit
…
various
abc9: uniquify blackboxes like whiteboxes (#2695)
2021-03-29 22:02:06 -07:00
verilog
sv: check validity of package end label
2021-05-10 14:37:32 -04:00
vloghtb
…
gen-tests-makefile.sh
tests: Parallelize
2020-09-21 15:07:02 +02:00