Martin Povišer 495a7805ec aiger2: Support $extern: hierarchy ...

`$extern:...` modules inserted by `techmap -extern` are special in the
regard that they have a private ID (starting with a dollar sign) but are
not an internal cell. Support those modules in xaiger export.

2024-12-10 14:27:29 +01:00

..

aiger

write_xaiger: Get by without endianness helpers

2024-09-03 08:59:09 +02:00

aiger2

aiger2: Support $extern: hierarchy

2024-12-10 14:27:29 +01:00

blif

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

btor

Merge pull request #4645 from georgerennie/george/btor_undef_array_init

2024-11-11 16:18:57 +01:00

cxxrtl

cxxrtl: use debug attrs of alias not aliasee

2024-11-12 13:07:33 +00:00

edif

Reduce comparisons of size_t and int

2024-11-29 12:53:29 +13:00

firrtl

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

functional

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

intersynth

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

jny

chore: fix master branch refs

2024-03-24 00:41:54 -04:00

json

add select option for write_json

2024-11-07 17:48:06 +08:00

rtlil

Remove references to ilang

2024-11-05 12:36:31 +13:00

simplec

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

smt2

Merge pull request #3953 from georgerennie/bug_3769

2024-11-11 16:23:35 +01:00

smv

Remove references to ilang

2024-11-05 12:36:31 +13:00

spice

Ignore $scopeinfo in write_spice

2024-02-06 17:51:29 +01:00

table

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

verilog

Simplify using module->ports, which is apparently sorted

2024-11-17 11:36:30 -08:00