Marcelina Kościelnicka 4a35f244aa quicklogic: Add .gitignore file for test outputs.

2021-03-23 17:35:00 +01:00

..

aiger

switch argument order to work with macOS getopt

2020-09-23 12:48:26 +02:00

arch

quicklogic: Add .gitignore file for test outputs.

2021-03-23 17:35:00 +01:00

asicworld

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bram

tests/bram: Do not generate write address collisions.

2021-03-08 16:53:03 +01:00

errors

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fsm

tests: fsm to use a randomly-generated seed

2020-04-24 14:31:33 -07:00

hana

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liberty

dfflibmap: Refactor to use dfflegalize internally.

2020-07-09 18:51:03 +02:00

lut

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memfile

Added 'set -e' into tests/memfile/run-test.sh

2020-02-06 10:45:40 -03:00

memories

tests: Parallelize

2020-09-21 15:07:02 +02:00

opt

opt_clean: Remove init attribute bits together with removed DFFs.

2021-03-15 17:16:53 +01:00

opt_share

tests: Parallelize

2020-09-21 15:07:02 +02:00

proc

proc_arst: Add special-casing of clock signal in conditionals.

2021-03-15 17:17:29 +01:00

realmath

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rpc

rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors

2020-03-06 15:29:01 +01:00

sat

assertpmux: Fix crash on unused $pmux output.

2021-02-22 23:30:28 +01:00

select

Merge pull request #1949 from YosysHQ/eddie/select_blackbox

2020-04-22 15:35:05 -07:00

share

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simple

verilog: fix buf/not primitives with multiple outputs

2021-03-17 11:44:03 -04:00

simple_abc9

Set aside extraneous tests in simple_abc9 test suite

2021-03-01 12:13:11 -05:00

smv

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sva

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svinterfaces

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svtypes

verilog: check entire user type stack for type definition

2021-03-21 19:35:13 -04:00

techmap

Add tests for some common techmap files.

2021-02-24 01:07:34 +01:00

tools

memory_dff: Remove now-useless write port handling.

2021-03-08 20:16:29 +01:00

unit

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various

blackbox: Include whiteboxed modules

2021-03-17 13:58:04 +00:00

verilog

sv: allow typenames as function return types

2021-03-19 12:08:43 -04:00

vloghtb

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gen-tests-makefile.sh

tests: Parallelize

2020-09-21 15:07:02 +02:00