Eddie Hung 4ae7f3a8ed Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor ...

opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs

2020-04-01 14:17:01 -07:00

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aiger

tests/aiger: Add missing .gitignore

2020-02-15 19:52:21 +01:00

arch

Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor

2020-04-01 14:17:01 -07:00

asicworld

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bram

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errors

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fsm

Speed up "make test" and related cleanups

2019-08-17 14:37:07 +02:00

hana

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liberty

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lut

Forgot to commit

2019-07-16 12:44:26 -07:00

memfile

Added 'set -e' into tests/memfile/run-test.sh

2020-02-06 10:45:40 -03:00

memories

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opt

Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor

2020-04-01 14:17:01 -07:00

opt_share

Support various binary operators in opt_share

2019-08-04 19:06:38 +02:00

proc

proc_clean: fix order of switch insertion.

2019-08-19 16:44:23 +00:00

realmath

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rpc

rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors

2020-03-06 15:29:01 +01:00

sat

Merge pull request #1638 from YosysHQ/eddie/fix1631

2020-02-05 19:31:18 +01:00

select

Do not warn on empty selection with prefixed arg_memb.

2020-03-23 17:50:11 +00:00

share

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simple

Add dynamic slicing Verilog testcase

2020-03-31 11:51:31 -07:00

simple_abc9

Update simple_abc9 tests

2020-02-27 10:17:29 -08:00

smv

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sva

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svinterfaces

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svtypes

Support module/package/interface/block scope for typedef names.

2020-03-23 20:07:22 +00:00

techmap

techmap: Fix cell names with _TECHMAP_REPLACE_.*

2020-03-23 11:17:07 +01:00

tools

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unit

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various

Add support for SystemVerilog-style `define to Verilog frontend

2020-03-27 16:08:26 +00:00

vloghtb

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