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YosysHQ.yosys/techlibs/xilinx
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Oliver Keszöcze fc56978703 Check DREG attribute 
The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
2023-02-17 17:54:41 +01:00
..
tests
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
abc9_model.v
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
arith_map.v
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
brams_defs.vh
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc2v_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc2v.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc3sda_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc3sda.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc4v_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc4v.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc5v_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc6v_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xcu_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xcv_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xcv.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
cells_map.v
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
cells_sim.v
Check DREG attribute
2023-02-17 17:54:41 +01:00
cells_xtra.py
xilinx: Add RAMB4* blackboxes
2022-03-21 13:11:52 +01:00
cells_xtra.v
xilinx: Add RAMB4* blackboxes
2022-03-21 13:11:52 +01:00
ff_map.v
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
lut_map.v
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
lutrams_xc5v_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams_xc5v.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams_xcu.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams_xcv_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams_xcv.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Makefile.inc
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
mux_map.v
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
synth_xilinx.cc
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
urams_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
urams.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
xc3s_mult_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc3sda_dsp_map.v
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
xc4v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc5v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc6s_dsp_map.v
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
xc7_dsp_map.v
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
2020-09-23 09:15:24 -07:00
xcu_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xilinx_dffopt.cc
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00