Claire Xenia Wolf fe9689c136 Fixed Verific parser error in ice40 cell library ...

non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode

2021-10-19 12:33:18 +02:00

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tests

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.gitignore

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abc9_model.v

Fix icestorm links

2021-06-09 12:39:12 +02:00

arith_map.v

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

brams_init.py

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brams_map.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

brams.txt

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cells_map.v

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cells_sim.v

Fixed Verific parser error in ice40 cell library

2021-10-19 12:33:18 +02:00

dsp_map.v

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ff_map.v

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ice40_braminit.cc

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

ice40_opt.cc

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

latches_map.v

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Makefile.inc

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synth_ice40.cc

opt_lut: Allow more than one -dlogic per cell type.

2021-07-29 17:30:07 +02:00