Clifford Wolf 0e0c80fac8 Add support for zero-width signals to Verilog back-end, fixes #948 ...

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2019-04-22 19:44:42 +02:00

..

Makefile.inc

initial import

2013-01-05 11:13:26 +01:00

verilog_backend.cc

Add support for zero-width signals to Verilog back-end, fixes #948

2019-04-22 19:44:42 +02:00