d3b6b7fe98
This test pretty much passes by accident — the `prep` command runs memory_collect without memory_dff first, which prevents merging read register into the memory, and thus blocks block RAM inference for a reason completely unrelated to the attribute. The attribute setting didn't actually work because it was set on the containing module instead of the actual memory.
46 lines
2.0 KiB
Plaintext
46 lines
2.0 KiB
Plaintext
# Check that blockram memory without parameters is not modified
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read_verilog ../common/memory_attributes/attributes_test.v
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hierarchy -top block_ram
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synth_xilinx -top block_ram -noiopad
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 1 t:RAMB18E1
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# Check that distributed memory without parameters is not modified
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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hierarchy -top distributed_ram
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synth_xilinx -top distributed_ram -noiopad
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cd distributed_ram # Constrain all select calls below inside the top module
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select -assert-count 8 t:RAM32X1D
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# Set ram_style distributed to blockram memory; will be implemented as distributed
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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setattr -set ram_style "distributed" block_ram/m:*
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synth_xilinx -top block_ram -noiopad
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 32 t:RAM128X1D
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# Set synthesis, logic_block to blockram memory; will be implemented as distributed
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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setattr -set logic_block 1 block_ram/m:*
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synth_xilinx -top block_ram -noiopad
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 0 t:RAMB18E1
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select -assert-count 32 t:RAM128X1D
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# Set ram_style block to a distributed memory; will be implemented as blockram
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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synth_xilinx -top distributed_ram_manual -noiopad
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cd distributed_ram_manual # Constrain all select calls below inside the top module
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select -assert-count 1 t:RAMB18E1
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# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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synth_xilinx -top distributed_ram_manual_syn -noiopad
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cd distributed_ram_manual_syn # Constrain all select calls below inside the top module
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select -assert-count 1 t:RAMB18E1
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