whitequark 4f426c2ac4 write_verilog: do not print (*init*) attributes on regs. ...

If an init value is emitted for a reg, an (*init*) attribute is never
necessary, since it is exactly equivalent. On the other hand, some
tools that consume Verilog (ISE, Vivado, Quartus) complain about
(*init*) attributes because their interpretation differs from Yosys.

All (*init*) attributes that would not become reg init values anyway
are emitted as before.

2019-09-22 16:52:06 +00:00

..

aiger

Recognise built-in types (e.g. $_DFF_*)

2019-08-30 20:15:09 -07:00

blif

RTLIL::S{0,1} -> State::S{0,1}

2019-08-07 11:12:38 -07:00

btor

Use State::S{0,1}

2019-08-06 16:22:47 -07:00

edif

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

firrtl

Merge pull request #1258 from YosysHQ/eddie/cleanup

2019-08-10 09:52:14 +02:00

ilang

RTLIL::S{0,1} -> State::S{0,1}

2019-08-07 11:12:38 -07:00

intersynth

substr() -> compare()

2019-08-07 12:20:08 -07:00

json

Implement improved JSON attr/param encoding

2019-08-01 12:34:52 +02:00

protobuf

Support filename rewrite in backends

2019-06-18 14:39:52 -07:00

simplec

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

2019-08-06 04:47:55 +02:00

smt2

substr() -> compare()

2019-08-07 12:20:08 -07:00

smv

substr() -> compare()

2019-08-07 12:20:08 -07:00

spice

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

table

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

verilog

write_verilog: do not print (*init*) attributes on regs.

2019-09-22 16:52:06 +00:00