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YosysHQ.yosys/kernel
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Charlotte 7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse 
See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
2023-08-11 04:46:52 +02:00
..
binding.cc
Generate an RTLIL representation of bind constructs
2021-08-13 17:11:35 -06:00
binding.h
Generate an RTLIL representation of bind constructs
2021-08-13 17:11:35 -06:00
bitpattern.h
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
calc.cc
Add bitwise $bweqx and $bwmux cells
2022-11-30 18:24:35 +01:00
cellaigs.cc
Merge pull request #3840 from povik/cellaigs-cmp-cells
2023-07-31 16:23:39 +02:00
cellaigs.h
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
celledges.cc
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
celledges.h
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
celltypes.h
celltypes: add $print
2023-08-11 04:46:52 +02:00
consteval.h
Remove set but unused variable
2022-05-27 12:37:03 +02:00
constids.inc
ast: translate $display/$write tasks in always blocks to new $print cell.
2023-08-11 04:46:52 +02:00
cost.h
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
driver.cc
add note to help about how to chain commands
2023-01-02 16:10:28 +01:00
ff.cc
Add the $anyinit cell and the formalff pass
2022-08-16 13:37:30 +02:00
ff.h
Add the $anyinit cell and the formalff pass
2022-08-16 13:37:30 +02:00
ffinit.h
Add new helper class for merging FFs into cells, use for memory_dff.
2021-05-23 14:46:59 +02:00
ffmerge.cc
Fix a regression from #3035.
2021-10-08 15:44:07 +02:00
ffmerge.h
Add new helper class for merging FFs into cells, use for memory_dff.
2021-05-23 14:46:59 +02:00
fmt.cc
fmt: remove lzero by lowering during Verilog parse
2023-08-11 04:46:52 +02:00
fmt.h
fmt: remove lzero by lowering during Verilog parse
2023-08-11 04:46:52 +02:00
fstdata.cc
Fixes for some of clang scan-build detected issues
2023-01-17 12:58:08 +01:00
fstdata.h
Start restoring memory state from VCD/FST
2022-05-04 10:41:04 +02:00
hashlib.h
Add recover_names pass to recover names post-mapping
2023-05-25 10:55:07 +02:00
json.cc
Support for BTOR witness to Yosys witness conversion
2023-01-11 18:07:16 +01:00
json.h
Support for BTOR witness to Yosys witness conversion
2023-01-11 18:07:16 +01:00
log.cc
Merge pull request #3839 from povik/python-log-newline
2023-07-24 16:28:02 +02:00
log.h
ast: Move to a new helper method to print input errors
2023-07-20 23:40:19 -04:00
macc.h
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
mem.cc
kernel/mem: Assert ABITS is not below wide_log2
2023-07-19 16:50:59 +02:00
mem.h
Add proc_rom pass.
2022-05-13 00:37:14 +02:00
modtools.h
remove template declaration that stops function from being used
2023-01-11 16:09:05 +01:00
qcsat.cc
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
qcsat.h
Refactor common parts of SAT-using optimizations into a helper.
2021-08-09 16:54:35 +02:00
register.cc
Fixes for some of clang scan-build detected issues
2023-01-17 12:58:08 +01:00
register.h
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
rtlil.cc
ast: translate $display/$write tasks in always blocks to new $print cell.
2023-08-11 04:46:52 +02:00
rtlil.h
kernel/rtlil: Trailing whitespace cleanup
2023-07-26 20:50:55 +01:00
satgen.cc
Add bitwise $bweqx and $bwmux cells
2022-11-30 18:24:35 +01:00
satgen.h
sat: Add -set-def-formal option to force defined $any* outputs
2022-11-28 14:50:52 +01:00
sigtools.h
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
timinginfo.h
sta: very crude static timing analysis pass
2021-11-25 17:20:27 +01:00
utils.h
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
yosys.cc
Fixes for some of clang scan-build detected issues
2023-01-17 12:58:08 +01:00
yosys.h
Fix tcl crash in case of error executing command
2022-11-30 15:54:31 +01:00
yw.cc
Remove a statement without effect.
2023-04-17 10:53:05 -07:00
yw.h
sim/formalff: Clock handling for yw cosim
2023-01-11 18:07:16 +01:00