This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-04-28 12:59:00 +00:00
Code
Issues
Releases
Wiki
Activity
Files
50f86c11b2bb9e561f5a0cf10e053b1aa4918abd
YosysHQ.yosys
/
frontends
/
verilog
History
David Shah
50f86c11b2
sv: Add lexing and parsing of .* (wildcard port conns)
...
Signed-off-by: David Shah <
dave@ds0.me
>
2020-02-02 16:12:33 +00:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Fix handling of z_digit "?" and fix optimization of cmp with "z"
2019-09-13 13:39:39 +02:00
Makefile.inc
Read bigger Verilog files.
2019-05-18 14:20:30 +03:00
preproc.cc
Fixed some missing "verilog_" in documentation
2019-12-13 10:17:05 -03:00
verilog_frontend.cc
Add "verilog_defines -list" and "verilog_defines -reset"
2019-10-21 13:35:56 +02:00
verilog_frontend.h
Add specify parser
2019-04-23 21:36:59 +02:00
verilog_lexer.l
sv: Add lexing and parsing of .* (wildcard port conns)
2020-02-02 16:12:33 +00:00
verilog_parser.y
sv: Add lexing and parsing of .* (wildcard port conns)
2020-02-02 16:12:33 +00:00
