Clifford Wolf 3d27c1cc80

Merge pull request #513 from udif/pr_reg_wire_error ...

Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)

2018-08-15 13:35:41 +02:00

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asicworld

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bram

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fsm

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hana

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memories

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realmath

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sat

Allow $size and $bits in verilog mode, actually check test case

2017-09-29 11:56:43 +02:00

share

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simple

reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files

2018-06-05 18:00:06 +03:00

smv

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sva

Major redesign of Verific SVA importer

2018-02-27 20:33:15 +01:00

techmap

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tools

Fixed typo (sikp -> skip)

2018-06-05 22:41:27 +03:00

unit

Build hotfix in tests/unit/Makefile

2016-12-11 10:58:49 +01:00

various

Modified errors into warnings

2018-06-05 18:03:22 +03:00

vloghtb

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