Marcelina Kościelnicka 347dd01c2f xilinx: Fix srl regression. ...

Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9.  Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.

2020-07-12 23:41:27 +02:00

..

achronix

Use C++11 final/override keywords.

2020-06-18 23:34:52 +00:00

anlogic

Use C++11 final/override keywords.

2020-06-18 23:34:52 +00:00

common

simcells: Fix reset polarity for $_DLATCH_???_ cells.

2020-06-30 15:32:06 +02:00

coolrunner2

Use C++11 final/override keywords.

2020-06-18 23:34:52 +00:00

easic

Use C++11 final/override keywords.

2020-06-18 23:34:52 +00:00

ecp5

ecp5: Use dfflegalize.

2020-07-05 18:49:41 +02:00

efinix

efinix: Use dfflegalize.

2020-07-06 12:28:17 +02:00

gowin

gowin: Use dfflegalize.

2020-07-06 12:27:46 +02:00

greenpak4

Use C++11 final/override keywords.

2020-06-18 23:34:52 +00:00

ice40

ice40: Use dfflegalize.

2020-07-05 05:12:09 +02:00

intel

Update dff2dffe, dff2dffs, zinit to new FF types.

2020-06-23 18:24:53 +02:00

intel_alm

intel_alm: direct M10K instantiation

2020-07-05 23:28:59 +02:00

sf2

sf2: Use dfflegalize.

2020-07-09 21:56:14 +02:00

xilinx

xilinx: Fix srl regression.

2020-07-12 23:41:27 +02:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00