Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, ...

meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.

2018-10-25 02:37:56 +03:00

..

ast

Merge pull request #659 from rubund/sv_interfaces

2018-10-18 10:58:47 +02:00

blif

Merge pull request #591 from hzeller/virtual-override

2018-08-15 14:05:38 +02:00

ilang

Add "make coverage"

2018-08-27 14:22:21 +02:00

json

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

liberty

Minor code cleanups in liberty front-end

2018-10-17 12:23:36 +02:00

verific

Improve Verific importer blackbox handling

2018-10-07 19:48:55 +02:00

verilog

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00