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YosysHQ.yosys/techlibs/ecp5/abc_model.v
2019-08-23 13:20:29 -07:00

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Verilog

// ---------------------------------------
(* abc_box_id=2 *)
module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
endmodule