github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-20 01:55:30 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/frontends/ast
History
Ruben Undheim a8200a773f A few modifications after pull request comments 
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
2016-06-18 14:23:38 +02:00
..
ast.cc
A few modifications after pull request comments
2016-06-18 14:23:38 +02:00
ast.h
Added support for SystemVerilog packages with localparam definitions
2016-06-18 10:53:55 +02:00
dpicall.cc
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
genrtlil.cc
Added support for SystemVerilog packages with localparam definitions
2016-06-18 10:53:55 +02:00
Makefile.inc
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
simplify.cc
Fixed access-after-delete bug in mem2reg code
2016-05-27 17:25:33 +02:00