Ruben Undheim 545bcb37e8 Allow defining input ports as "input logic" in SystemVerilog

2016-06-20 20:16:37 +02:00

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ast

A few modifications after pull request comments

2016-06-18 14:23:38 +02:00

blif

Added "read_blif -sop"

2016-06-18 12:33:13 +02:00

ilang

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

liberty

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

verific

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

verilog

Allow defining input ports as "input logic" in SystemVerilog

2016-06-20 20:16:37 +02:00

vhdl2verilog

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00