Clifford Wolf 54d74cf616 Added freduce -dump

2014-03-06 22:06:58 +01:00

..

eval.cc

Added generic RTLIL::SigSpec::parse_sel() with support for selection variables

2014-02-06 19:22:46 +01:00

example.v

Added support for shifter cells to SAT generator

2013-06-08 15:12:08 +02:00

example.ys

Renamed "sat_solve" pass to "sat"

2013-06-09 21:55:53 +02:00

expose.cc

Various improvements in expose command (added -sep and -cut)

2014-02-09 11:07:46 +01:00

freduce.cc

Added freduce -dump

2014-03-06 22:06:58 +01:00

Makefile.inc

Added expose command

2014-02-05 23:59:55 +01:00

miter.cc

Added miter -make_outcmp

2014-02-06 02:20:55 +01:00

sat.cc

Added "sat -dump_cnf"

2014-02-18 09:29:08 +01:00