Clifford Wolf 27a872d1e7 Added support for "upto" wires to Verilog front- and back-end

2014-07-28 14:25:03 +02:00

..

autotest

Refactoring: Renamed RTLIL::Design::modules to modules_

2014-07-27 11:18:30 +02:00

blif

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

btor

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

edif

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

ilang

Added wire->upto flag for signals such as "wire [0:7] x;"

2014-07-28 12:12:13 +02:00

intersynth

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

spice

Using log_assert() instead of assert()

2014-07-28 11:27:48 +02:00

verilog

Added support for "upto" wires to Verilog front- and back-end

2014-07-28 14:25:03 +02:00