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58b1522a20ef9a4ec914280bcaf4f4e637f4368e
YosysHQ.yosys
/
techlibs
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intel
History
Richard Herveille
58b1522a20
Added DSP macros
2024-03-06 02:45:29 +01:00
..
common
Fixed data/address width parameters
2024-03-06 02:45:07 +01:00
cyclone10lp
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneiv
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneive
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
max10
Added DSP macros
2024-03-06 02:45:29 +01:00
Makefile.inc
synth_intel: Remove incomplete Arria 10 GX support.
2020-08-21 01:46:06 +02:00
synth_intel.cc
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
