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YosysHQ.yosys
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frontends
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verilog
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Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Makefile.inc
Read bigger Verilog files.
2019-05-18 14:20:30 +03:00
preproc.cc
Support SystemVerilog `` extension for macros
2018-05-17 00:09:56 -04:00
verilog_frontend.cc
Add "read_verilog -pwires" feature,
closes
#1106
2019-06-19 14:38:50 +02:00
verilog_frontend.h
Add specify parser
2019-04-23 21:36:59 +02:00
verilog_lexer.l
verilog_lexer: Increase YY_BUF_SIZE to 65536
2019-07-26 13:35:39 +01:00
verilog_parser.y
substr() -> compare()
2019-08-07 12:20:08 -07:00