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YosysHQ.yosys/passes
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Clifford Wolf 30f1ac7ce9 Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:51:53 +02:00
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cmds
Fix select command error msg, fixes issue #1081
2019-09-01 11:00:09 +02:00
equiv
Spelling
2019-08-22 16:06:36 -07:00
fsm
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
hierarchy
Adopt @cliffordwolf's suggestion
2019-09-03 12:18:50 -07:00
memory
stoi -> atoi
2019-08-07 11:09:17 -07:00
opt
Copy-paste typo
2019-08-22 08:43:44 -07:00
pmgen
Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc
2019-09-01 10:11:33 -07:00
proc
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
sat
Add $dlatch support to async2sync
2019-08-28 09:45:22 +02:00
techmap
Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220
2019-09-05 13:51:53 +02:00
tests
More use of IdString::in()
2019-08-15 09:23:57 -07:00