Eddie Hung 25b1670a84 Rename boxes too

2019-08-29 07:03:32 -07:00

..

tests

Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"

2019-08-12 12:06:45 -07:00

.gitignore

Initialization support for all iCE40 bram modes

2015-04-26 08:39:31 +02:00

abc_hx.box

Rename boxes too

2019-08-29 07:03:32 -07:00

abc_hx.lut

Fix rename

2019-04-18 09:04:34 -07:00

abc_lp.box

Rename boxes too

2019-08-29 07:03:32 -07:00

abc_lp.lut

Rename to abc_*.{box,lut}

2019-04-18 09:02:58 -07:00

abc_u.box

Rename boxes too

2019-08-29 07:03:32 -07:00

abc_u.lut

Rename to abc_*.{box,lut}

2019-04-18 09:02:58 -07:00

arith_map.v

Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"

2019-08-12 12:06:45 -07:00

brams_init.py

Switched to Python 3

2015-08-22 09:59:33 +02:00

brams_map.v

ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

2019-02-28 16:23:40 -08:00

brams.txt

Added read-enable to memory model

2015-09-25 12:23:11 +02:00

cells_map.v

Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER

2019-08-12 12:19:25 -07:00

cells_sim.v

Trailing comma

2019-08-28 17:25:54 -07:00

ice40_braminit.cc

substr() -> compare()

2019-08-07 12:20:08 -07:00

ice40_ffinit.cc

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

ice40_ffssr.cc

ice40: Honor the "dont_touch" attribute in FFSSR pass

2018-12-08 22:46:28 +01:00

ice40_opt.cc

Do not overwrite LUT param

2019-08-28 18:46:53 -07:00

latches_map.v

Added synth_ice40 support for latches via logic loops

2016-05-06 23:02:37 +02:00

Makefile.inc

Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"

2019-08-12 12:06:45 -07:00

synth_ice40.cc

Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"

2019-08-12 12:06:45 -07:00