Eddie Hung 593e4a30bb MUXF78 -> $__MUXF78 to indicate internal

2019-06-26 20:09:28 -07:00

..

tests

…

.gitignore

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abc_xc7_nowide.lut

Add _nowide variants of LUT libraries in -nowidelut flows

2019-06-26 10:23:29 -07:00

abc_xc7.box

MUXF78 -> $__MUXF78 to indicate internal

2019-06-26 20:09:28 -07:00

abc_xc7.lut

Simplify comment

2019-06-17 19:14:41 -07:00

arith_map.v

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brams_bb.v

Remove WIP ABC9 flop support

2019-06-14 10:37:52 -07:00

brams_init.py

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brams_map.v

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brams.txt

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cells_map.v

This optimisation doesn't seem to work...

2019-06-25 09:21:46 -07:00

cells_sim.v

Merge remote-tracking branch 'origin/xaig' into xc7mux

2019-06-26 20:07:31 -07:00

cells_xtra.sh

Merge remote-tracking branch 'origin/master' into xaig

2019-06-25 09:33:11 -07:00

cells_xtra.v

Merge remote-tracking branch 'origin/master' into xaig

2019-06-25 09:33:11 -07:00

drams_map.v

Add RAM32X1D support

2019-06-24 16:16:50 -07:00

drams.txt

Add RAM32X1D support

2019-06-24 16:16:50 -07:00

ff_map.v

Cleanup

2019-06-05 12:28:46 -07:00

lut_map.v

Really permute Xilinx LUT mappings as default LUT6.I5:A6

2019-06-18 11:48:48 -07:00

Makefile.inc

Revert "Remove wide mux inference"

2019-06-14 12:50:24 -07:00

mux_map.v

Change synth_xilinx's -nomux to -minmuxf <int>

2019-06-24 10:04:01 -07:00

synth_xilinx.cc

synth_xilinx's muxcover call to be very conservative -- -nodecode

2019-06-26 17:57:10 -07:00