Miodrag Milanovic b70f527c67 verific: fixed -sv2017 option and added ability to set VHDL standard if applicable

2026-01-29 10:32:30 +01:00

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aiger

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aiger2

Enable xaiger2 pass when not in NDEBUG

2025-11-21 14:23:32 -08:00

ast

verilog: Do not set module_not_derived on internal cells

2026-01-19 16:48:13 -08:00

blif

Add gatesi_mode in BLIF format

2026-01-14 21:41:56 +01:00

json

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liberty

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rpc

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rtlil

Add -legalize option to read_rtlil

2025-12-21 21:47:48 +00:00

verific

verific: fixed -sv2017 option and added ability to set VHDL standard if applicable

2026-01-29 10:32:30 +01:00

verilog

read_verilog: remove log I left behind by accident

2026-01-13 18:47:23 +01:00