YosysHQ.yosys/techlibs/lattice/lutrams_trellis.txt

ram distributed $__TRELLIS_DPR16X4_ {
	abits 4;
	width 4;
	cost 4;
	init any;
	prune_rom;
	port sw "W" {
		clock anyedge;
	}
	port ar "R" {
	}
}