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5d1ce043812b9b86ee3c3588c430ea1cd57fee1e
YosysHQ.yosys
/
techlibs
/
xilinx
History
Eddie Hung
5d1ce04381
Add support for {A,B,P}REG in DSP48E1
2019-07-16 14:05:50 -07:00
..
tests
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.gitignore
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abc_xc7_nowide.lut
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abc_xc7.box
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abc_xc7.lut
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arith_map.v
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brams_init.py
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cells_map.v
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cells_sim.v
Add support for {A,B,P}REG in DSP48E1
2019-07-16 14:05:50 -07:00
cells_xtra.sh
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cells_xtra.v
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drams_map.v
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drams.txt
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dsp_map.v
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ff_map.v
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lut_map.v
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Makefile.inc
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mux_map.v
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synth_xilinx.cc
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xc6s_brams_bb.v
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xc6s_brams_map.v
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xc6s_brams.txt
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xc7_brams_bb.v
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xc7_brams_map.v
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xc7_brams.txt
…
