Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections ...

- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change

2021-10-25 18:25:50 -07:00

..

.gitignore

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aes_kexp128.v

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always01.v

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always02.v

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always03.v

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arraycells.v

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arrays01.v

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arrays02.sv

Add proper test for SV-style arrays

2019-06-20 12:06:07 +02:00

asgn_binop.sv

sv: support remaining assignment operators

2021-05-25 16:15:57 -04:00

attrib01_module.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

attrib02_port_decl.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

attrib03_parameter.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

attrib04_net_var.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

attrib05_port_conn.v.DISABLED

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

attrib06_operator_suffix.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

attrib07_func_call.v.DISABLED

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

attrib08_mod_inst.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

attrib09_case.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

carryadd.v

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case_expr_const.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

case_expr_non_const.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

case_large.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

const_branch_finish.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

const_fold_func.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

const_func_shadow.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

constmuldivmod.v

Expand tests/simple/constmuldivmod.v

2020-05-28 22:59:04 +02:00

constpower.v

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defvalue.sv

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

dff_different_styles.v

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dff_init.v

Add test case from #997

2019-05-07 19:58:04 +02:00

dynslice.v

Add dynamic slicing Verilog testcase

2020-03-31 11:51:31 -07:00

fiedler-cooley.v

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forgen01.v

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forgen02.v

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forloops.v

Add additional test cases for for-loops

2019-05-01 09:32:07 +02:00

fsm.v

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func_block.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

func_recurse.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

func_width_scope.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

genblk_collide.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

genblk_dive.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

genblk_order.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

genblk_port_shadow.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

generate.v

Merge pull request #2529 from zachjs/unnamed-genblk

2021-02-04 09:57:28 +00:00

graphtest.v

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hierarchy.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

hierdefparam.v

Fix handling of defparam for when default_nettype is none

2019-02-24 20:09:41 +01:00

i2c_master_tests.v

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ifdef_1.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

ifdef_2.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

implicit_ports.v

Rename implicit_ports.sv test to implicit_ports.v

2019-06-07 13:12:25 +02:00

local_loop_var.sv

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

localparam_attr.v

Added tests for Verilog frontent for attributes on parameters and localparams

2019-05-16 12:53:43 +02:00

loop_prefix_case.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

loop_var_shadow.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

loops.v

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macro_arg_spaces.sv

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

macro_arg_surrounding_spaces.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

macros.v

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matching_end_labels.sv

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

mem2reg_bounds_tern.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

mem2reg.v

Add splitcmplxassign test case and silence splitcmplxassign warning

2019-05-01 10:01:54 +02:00

mem_arst.v

Make SV2017 compliant courtesy of @wsnyder

2019-12-12 07:34:07 -08:00

memory.v

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memwr_port_connection.sv

verilog: use derived module info to elaborate cell connections

2021-10-25 18:25:50 -07:00

module_scope_case.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

module_scope.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

multiplier.v

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muxtree.v

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named_genblk.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

nested_genblk_resolve.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

omsp_dbg_uart.v

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operators.v

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param_attr.v

Added tests for Verilog frontent for attributes on parameters and localparams

2019-05-16 12:53:43 +02:00

paramods.v

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partsel.v

Bugfix in partsel.v signed indices test cases

2020-05-02 11:21:01 +02:00

process.v

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realexpr.v

Add test case for real parameters

2019-08-20 11:38:21 +02:00

repwhile.v

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retime.v

Add retime test

2019-04-05 16:28:46 -07:00

rotate.v

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run-test.sh

tests/simple: remove "nullglob" shopt

2020-09-21 15:07:02 +02:00

scopes.v

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signed_full_slice.v

verilog: use derived module info to elaborate cell connections

2021-10-25 18:25:50 -07:00

signedexpr.v

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sincos.v

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specify.v

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string_format.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

subbytes.v

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task_func.v

Fix handling of task output ports in clocked always blocks, fixes #857

2019-03-07 22:44:37 -08:00

undef_eqx_nex.v

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unnamed_block_decl.sv

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

usb_phy_tests.v

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values.v

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verilog_primitives.v

verilog: fix buf/not primitives with multiple outputs

2021-03-17 11:44:03 -04:00

vloghammer.v

More deadname stuff

2021-06-09 12:33:41 +02:00

wandwor.v

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

wreduce.v

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xfirrtl

Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.

2019-07-31 09:27:38 -07:00